Pad cells or pads facilitate the interface between the macroscopic world of BNC cables, lab benches, manual and automated handling equipment, oscilloscopes, and signal generators and the microscopic world of the core of an integrated circuit. Output pads include buffers with current driving capability sufficient to drive off-chip loads with the desired transient response. Input and Input/Output (IO) pads include some measure of protection against damage due to an electrostatic discharge (ESD) event. Further information on pads and ESD protection can be found in Chapter 18, pages 657-660 of “Design of Analog CMOS Integrated Circuits” International Edition 2001 as published by McGraw Hill, the contents of which are incorporated by reference.
As is described in U.S. Pat. No. 5,751,525, co-assigned to the assignee of the present invention and incorporated herein by reference, integrated circuits are vulnerable to electrical overstress (EOS). EOS results from an external source discharging large transient voltages onto one or more pins of an integrated circuit. These transient voltages can include very fast transients such as those produced by an electrostatic discharge (ESD) event, or slower transients such as may result from power-line surges.
ESD events can have differing characteristics due to the equivalent circuitry present. The human body model (HBM) correlates to a human-induced ESD event. The machine model (MM) correlates to a machine-induced ESD event. The field-induced charge device model (FICDM) relates to an ESD event induced by the discharge of the device through a pin.
ESD is a well-known cause of failure in integrated circuits (ICs), especially integrated circuits manufactured using MOS processes, but also, albeit to a lesser extent, those produced by bipolar processes. MOS devices sustain two types of permanent damage as a result of ESD. In MOS devices, the thin oxide layer of input gates cannot support high voltages without incurring damage. Where the input voltage across a diode junction becomes excessive, breakdown damage will occur when the EOS current becomes excessive. Secondly, the source/drain junction diodes may get damaged if they carry a large current in forward or reverse bias, thereby creating a short to the bulk (well) of the device or creating an open circuit. This diode junction breakdown occurs in both bipolar junction transistor (BJT) and MOS devices. Input protection circuits are frequently used in integrated circuits to protect against such failures and are normally provided within a pad cell so as to prevent the ESD interfacing with and corrupting the circuitry of the main portion of the integrated circuit. In addition to U.S. Pat. No. 5,751,525, U.S. Pat. Nos. 5,602,409 and 6,236,087 both describe a number of exemplary protection circuits that may be provided to obviate the effect of ESD within an IC environment.
It is also known that a pad cell may be provided with two or more signal paths for interfacing with the internal circuitry of the IC. Typically, a first signal path is operable for normal operating conditions and the second signal path is effective by specific input signals applied to the input pin of the IC. A reason for such multiple signal paths is to enable dual or multiple usage of the same input pin of the IC. It will be appreciated that when an IC is to be operated in test mode or some other non-normal application that it is sometimes necessary to access hardware and/or functions within the IC that is, or are, normally not used. To obviate the need to provide a specific input pin to enable this interface, it is common to provide a pin with multiple configurations such that it may be re-configured into a test mode if required. This ensures that a packaged IC is not provided with redundant pins, and as such the area of the chip can be reduced. Similarly, if the circuitry is to be used in JTAG (Joint Test Action Group) boundary scan testing or similar environment where a hardware method of talking to memory and flash without requiring any application running on the hardware is implemented, then it is important that there is provided a methodology for interfacing with the specific circuits of the IC without requiring additional pins.
A further example of multiple pin usage is three-state bus and IO usage. In this case, the pin function can alternate between read and a write functions, as defined by a shared RD/WR input.
Yet another example of multiple pin usages are devices, such as the Analog Devices ADμC812 product, which have user-definable pin interface re-configuration so that a user can define how the interface pins are to be used, depending on the application or specific requirement at the time.
There is therefore a need to provide an interface to an integrated circuit package that enables multiple pin functionality yet does not lead to current leakage within the circuit. There is additionally a need to provide a circuit that can operate with and in parallel to known ESD protection circuits to provide alternative communication input paths from a pin to circuitry within the IC so as to maximize the usage of the pin(s), reduce pin count, package area, package cost and the number of PCB signals required.